High speed encryption Engines
Encryption enabled DBMS
FPGA based SOC applications with encryption/decryption requirement
Other Features
Three architectures - General, Pipelined ands Serial
Fully tested & verified architecture
Verified on Xilinx FPGAs
FPGA efficient arithmetic blocks are used for high performance
Chosen IDEA core with FPGA board can also be provided
Brief Description:
International Data Encryption Algorithm (IDEA) is a block cipher that uses a 128-bit key to encrypt 64-bit data blocks. The 52 subkeys are all generated from the 128-bit original key. IDEA algorithm uses 52, 16-bit key sub-blocks, i.e. six subkeys for each of the first eight rounds and four more for the ninth round of output transformation. The following figure shows encryption and decryption with 52 subkeys. The figure.1 shows the steps involved in encryption
Figure .1 IDEA encryption and decryption
The rounds of IDEA involve complex mathematical operations, which makes it more secured encryption scheme. The figure.2 shows the steps involved in one round of IDEA algorithm.
Figure 2. The steps involved in one round of IDEA algorithm
The design methodology behind the IDEA algorithm is based on mixing three different operations. These operations are:
The IDEA core is available in three different architectures
General implementation
Pipelined implementation
Serial Implementation.
The pipelined implementation is the IDEA architecture which is implemented with a pipeline at every stage output, to improve the performance and hence throughput. The Serial architecture is optimized for area and gives low throughput. The figure 3 gives the serial architecture details.
Figure 3. IDEA Serial architecture.
For performance comparison and other details request the data sheet.
High speed encryption Engines
Encryption enabled DBMS
FPGA based SOC applications with encryption/decryption requirement.
Other Features
Fully tested & verified architecture
Verified on Xilinx FPGAs
FPGA efficient arithmetic blocks are used for high performance.
Hardware solution with chosen FPGA family can also be provided.
